As shown in FIG. 1a, a memory unit cell 1 is composed of a steering element 3 and a storage element 5 connected in series between a bit line 7 and a word line 9. Herner et al., U.S. patent application Ser. No. 10/955,549 filed Sep. 29, 2004 (which corresponds to US Published Application 2005/0052915 A1), Herner et al., U.S. patent application Ser. No. 11/015,824 filed Dec. 17, 2004, and U.S. patent application Ser. No. 11/819,078 filed Jul. 25, 2007, each hereby incorporated by reference, describe a three dimensional memory array which comprises memory cells with pillar shaped semiconductor junction diodes as the steering elements. As shown in FIG. 1a, this steering element 3 made from a diode has two terminals, and can be used with any two-terminal storage element 5. The diode 3 is shown in more detail in FIG. 1b, and contains an n+ region 11, an intrinsic region 13, and a p+ region 15, and is referred to a p-i-n diode. This vertical architecture can be used in a one time programmable (OTP) memory product with a higher density and simpler architecture and process. With relentless scaling requirement in the semiconductor industry, especially in the memory area, power consumption is one of biggest challenges. The conventional p-i-n diode 3 suffers relatively high reverse leakage due to a large depletion region.